1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a nonvolatile ferroelectric memory and a method for fabricating the same.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory CRAM) has a data processing speed equal to a dynamic random access memory DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1 shows hysteresis loop of a general ferroelectric. As shown in FIG. 1, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory device will now be described. FIG. 2 shows unit cell of a related art nonvolatile ferroelectric memory.
As shown in FIG. 2, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T1 with a gate connected with the wordline and a source connected with the bitline, and a ferroelectric capacitor FC1. A first terminal of the ferroelectric capacitor FC1 is connected with a drain of the transistor T1 and second terminal is connected with the plate line P/L.
The data input/output operation of the related art nonvolatile ferroelectric memory device will now be described. FIG. 3a is a timing chart illustrating the operation of the write mode of the related art nonvolatile ferroelectric memory device, and FIG. 3b is a timing chart illustrating the operation of read mode thereof.
During the write mode, an externally applied chip enable signal CSBpad is activated from high state to low state. At the same time, if a write enable signal WEBpad is applied from high state to low state, the write mode starts. Subsequently, if address decoding in the write mode starts, a pulse applied to a corresponding wordline is transmitted from low state to high state to select a cell.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is maintained at high state. To write a logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline.
In other words, a high signal is applied to the bitline, and if the low signal is applied to the plate line in a period where the signal applied to the wordline is high, a logic value xe2x80x9c1xe2x80x9d is written in the ferroelectric capacitor. A low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value xe2x80x9c0xe2x80x9d is written in the ferroelectric capacitor.
The reading operation of data stored in a cell by the above operation of the write mode will now be described. If an externally applied chip enable signal CSBpad is activated from high state to low state, all of bitlines become equipotential to low voltage by an equalizer signal EQ before a corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transmitted to the high signal in the corresponding wordline according to the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destroy data corresponding to the logic value xe2x80x9c1 xe2x80x9d stored in the ferroelectric memory. If the logic value xe2x80x9c0xe2x80x9d is stored in the ferroelectric memory, the corresponding data is not destroyed.
The destroyed data and the data that is not destroyed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. In other words, if the data is destroyed, the xe2x80x9cdxe2x80x9d state is transmitted to an xe2x80x9cfxe2x80x9d state as shown in hysteresis loop of FIG. 1. If the data is not destroyed, xe2x80x9caxe2x80x9d state is transmitted to the xe2x80x9cfxe2x80x9d state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value xe2x80x9c1xe2x80x9d is output in case that the data is destroyed while the logic value xe2x80x9c0xe2x80x9d is output in case that the data is not destroyed.
As described above, after the sensing amplifier outputs data, to recover the data to the original data, the plate line becomes inactive from high state to low state at the state that the high signal is applied to the corresponding wordline.
FIG. 4 is a block diagram showing the related art nonvolatile ferroelectric memory device. As shown in FIG. 4, the related art nonvolatile ferroelectric memory device includes a main cell array 41, a reference cell array 42 assigned on a lower part of the main cell array 41, a wordline driver 43 formed at a side of the main cell array for applying a driving signal to the main cell array 41 and the reference cell array 42, and a sense amplifier unit 44 formed at a lower part of the reference cell array 42. The wordline driver 43 applies the driving signal to a main wordline of the main cell array 41 and a reference wordline of the reference cell array 42. The sense amplifier unit 44 includes a plurality of sensing amplifiers and amplifies signals of a corresponding bitline B/L and bit bar line BB/L.
The operation of the related art nonvolatile ferroelectric memory device will now be described with reference to FIG. 5. FIG. 5 is a partially detailed view of FIG. 4. As shown in the drawing, the main cell array has a folded bitline structure in the same manner as DRAM.
Also, the reference cell array 42 has a folded bitline structure and includes a reference cell wordline and a reference cell plate line in pairs. At this time, reference cell wordline and the reference cell plate line pairs are defined as RWL_Nxe2x88x921 and RPL_Nxe2x88x921, and RWL_N and RPL_N, respectively.
When the main cell wordline WL_Nxe2x88x921 and the main cell plate line PL_Nxe2x88x921 are activated, the reference cell wordline RWL_Nxe2x88x921 and the reference cell plate line RPL_Nxe2x88x921 are activated. Therefore, data in the main cell is loaded into the bitline B/L and data in the reference cell is loaded into the bit bar line BB/L.
When the main cell wordline WL_N and the main cell plate line PL_N are activated, the reference cell wordline RWL_N and the reference cell plate line RPL_N are activated. Therefore, data in the main cell is loaded into the bit bar line BB/L and data in the reference cell is loaded into the bitline B/L.
A reference voltage REF by the reference cell exists between the bitline levels B_H(high) and B_Low) by the main cell. To generate the reference voltage REF between the bitline levels B_H and B_L, the logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d may be stored in a capacitor of the reference cell. When the logic value xe2x80x9c1xe2x80x9d is stored in the capacitor of the reference cell, the size of the capacitor of the reference cell is smaller than that of the capacitor of the main cell. When the logic value xe2x80x9c0xe2x80x9d is stored in the capacitor of the reference cell, the size of the capacitor of the reference cell is greater than that of the capacitor of the main cell. Thus, the related art nonvolatile ferroelectric memory can produce a reference voltage required by the sense amplifier unit 44 by using these two methods.
As described above, the related art nonvolatile ferroelectric memory has various disadvantages. When a capacitor size of the reference cell is made smaller than a capacitor size of the main cell to provide a level of the reference voltage to be between the bitline levels B_H and B_L and the reference cell capacitor is excessively switched, in comparison to the main cell, the reference cell experiences fatigue before the main cell, which makes the reference voltage unstable. When a capacitor size of the reference cell is made larger than a capacitor size of the main cell to provide the reference voltage to be between the bitline levels B_H and B_L, the capacitor size is larger.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a nonvolatile ferroelectric memory and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a nonvolatile ferroelectric memory and a method for fabricating the same that has a ferroelectric material for a gate insulating film in a gate electrode of a memory cell.
Another object of the present invention is to provide a nonvolatile ferroelectric memory and a method for fabricating the same that has three electrodes coupled together between first and second crossing signal lines in a memory cell.
Another object of the present invention is to provide a nonvolatile ferroelectric memory and a method for fabricating the same that reduces fatigue caused by the repetitive switching.
Another object of the present invention is to provide a nonvolatile ferroelectric memory and a method for fabricating the same that drops an operational voltage.
Another object of the present invention is to provide a nonvolatile ferroelectric memory and a method for fabricating the same that increases an operational speed.
Another object of the present invention is to provide a nonvolatile ferroelectric memory and a method for fabricating the same that reduces fatigue of a reference capacitor, drops an operations voltages and increases an operational speed.
To achieve at least these objects and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, the nonvolatile ferroelectric memory includes a plurality of wordlines formed in one direction, a plurality of pairs each having a control line and a sensing line formed in a direction crossing the wordlines at fixed intervals, first transistors each formed between every pair of the control line and the sensing line having a drain applied of a power source voltage and a gate dielectric film formed of a ferroelectric material, second transistors each having a drain connected to the sensing line, a source connected to a source of the first transistor, and a gate connected to the wordline, and third transistors each having a drain connected to the control line, a source connected to a gate of the first transistor, and a gate connected to the wordline.
To further achieve the above objects in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a method for fabricating a nonvolatile ferroelectric memory includes (1) forming a first insulating layer at a depth in a semiconductor substrate in a horizontal direction, and forming a second insulating layer arranged from a surface of the substrate to ends of the first insulating layer, to define the semiconductor substrate as a first substrate and a second substrate, (2) forming a first gate electrode over the first substrate with a ferroelectric material disposed inbetween, (3) forming a second gate electrode and a third gate electrode over the second substrate on both sides of the first substrate, each with a gate insulating film disposed inbetween, (4) forming first source/drain regions of a conduction type opposite to the first substrate in the first substrate on both sides of the first gate electrode, (5) forming second, and third source/drain regions of a conduction type opposite to the second substrate in the second substrate on both sides of the second and third gate electrodes, and (6) forming a first impurity region of a conduction type identical to the first substrate in the first substrate on one side of the first source impurity region.
To further achieve the above objects in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a memory device, comprising a plurality of first signal lines extending along a first direction, a plurality of second signal lines extending along a second direction to cross the first signal lines at prescribed intervals, a memory array having memory cells corresponding to intersections of the first signal lines and the second signal lines, a driver coupled to the first signal lines, a decoder coupled to the second signal lines, a sensing circuit coupled to the second signal lines to output data from the memory array, wherein each memory cell includes a transistor having a gate insulating layer of a gate electrode being a material that exhibits a residual polarization after application of an electric field.
To further achieve the above objects in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a memory device, comprising a plurality of first signal lines extending along a first direction, a plurality of second signal line pairs extending along a second direction to cross the first signal lines at prescribed intervals, a memory array having unit cells corresponding to intersections of the first signal lines and the second signal line pairs, a driver coupled to the first signal lines, a decoder coupled to the second signal lines, a sensing circuit coupled to the second signal lines to output data from the memory array, wherein a unit cell comprises, a first transistor coupled between a first pair of the second signal line pairs having a second electrode coupled to a first reference voltage, a second transistor having a second electrode coupled to one of the first pair of the second signal line pairs, a first electrode coupled to a first electrode of the first transistor, and a control electrode coupled to a corresponding first signal line; and a third transistor having a second electrode coupled to the other one of the first pair of the second signal line pairs, a first electrode coupled to a control electrode of the first transistor, and a control electrode coupled to the corresponding first signal line.
To further achieve the above objects in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a storage device, comprising a plurality of first signal lines extending along a first direction, a plurality of second signal lines extending along a second direction to cross the first signal lines at prescribed intervals, a plurality of cells corresponding to intersections of the first signal lines and the second signal lines, wherein the cells include a transistor having a gate insulating layer of a gate electrode being a material that has a residual polarization characteristic.
To further achieve the above objects in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a storage device, comprising a plurality of first signal lines extending along a first direction, a plurality of second signal line pairs extending along a second direction to cross the first signal lines at prescribed intervals, a storage cell coupled at a corresponding intersection of the first signal lines and the pairs of second signal lines, wherein the storage cell comprises, a first transistor coupled between each pair of the second signal line pairs having a second electrode coupled to a first reference voltage, a second transistor having a second electrode coupled to one of the second signal line pairs, a first electrode coupled to a first electrode of the first transistor, and a control electrode coupled to a corresponding first signal line, and a third transistor having a second electrode coupled to the other one of the second signal line pairs, a first electrode coupled to a control electrode of the first transistor, and a control electrode coupled to the corresponding first signal line.
To further achieve the above objects in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a nonvolatile ferroelectric memory, comprising a semiconductor substrate, an insulating layer that divides the substrate into first, second and third regions, a first gate electrode over a ferroelectric material over the first region of the substrate, a second and a third gate electrodes over second and third gate insulating films that are respectively over the second and third regions of the substrate on opposite sides of the first gate electrode, first source/drain regions in the first region of the substrate on both sides of the first gate electrode, and second and third source/drain regions in the respective second and third regions of the substrate on both sides of the second and third gate electrodes.
To further achieve the above objects in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a semiconductor memory device, comprising a semiconductor substrate, a first gate electrode on a first gate insulating film over a first region of the substrate, a second gate electrode and a third gate electrode over second and third regions of the substrate, respectively, each with a gate insulating film disposed therebetween, first source/drain regions in the first region of the substrate on both sides of the first gate electrode, second and third source/drain regions on both sides of the second and third gate electrodes in the second and third regions of the substrate, respectively, a first interconnection layer that provides a first reference voltage to the first drain region, a second interconnection layer that electrically couples the first source region to the second source region, and a third interconnection layer that electrically couples the first gate electrode and the third source region.
To further achieve the above objects in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a method for fabricating a nonvolatile ferroelectric memory, comprising forming a semiconductor substrate, forming a first gate electrode over a ferroelectric gate insulating film disposed over a first region of the substrate, forming a second gate electrode and a third gate electrode over second and third regions of the substrate, respectively, each with a gate insulating film disposed therebetween, forming first source/drain regions in the first region of the substrate on both sides of the first gate electrode, and forming second and third source/drain regions on both sides of the second and third gate electrodes in the second and third regions of the substrate, respectively.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.